Different design approaches for the RTES project are reviewed in this module including the "shot gun" start, where clock ticks are detected once at the start, the full synchronome continuous tick detection approach, and different options for implementation. RTES project designers must decide on a camera interface, for example a V4L2 (Video for Linux 2) interface to UVC (Universal Video Controller) driver, or an OpenCV interface to a camera.

To ensure that a real-time design is properly implemented, timing analysis based upon system logging and tracing must be used to verify that actual timing compared to theoretical RMA. This module provides and overview of methods and suggests the most efficient methods to debug and verify timing of the RTES project. The module includes a 1 Hz peer review of design and code to assist with RTES project improvement for external clock synchronization using camera images with a ticking analog clock.

This module covers methods of tracing and profiling for the overall RTES project platform including networking, system profiling, and methods to trace real-time services in particular. The module includes a 10 Hz peer review of design and code to assist with RTES project improvement for external clock synchronization with a digital stopwatch at this higher rate compared to 1 Hz.

The overall RTES project should be completed for this module. Students can review tips and examples for how to prepare their design materials, their RMA, and code for review. The process for inspection to verify and validate the design based upon the RTES project rubric is defined here as well.